As the need for integrated circuits for semiconductor devices having higher performance and greater functionality increases, device feature geometries continue to decrease. As device geometries become smaller, the dielectric constant of an insulating material used between conducting paths becomes an increasingly important factor in device performance.
As device dimensions shrink to less than 0.25 μm, propagation delay, cross-talk noise and power dissipation due to resistance-capacitance (RC) coupling become significant due to increased wiring capacitance, especially interline capacitance between parallel metal lines on the same level. These factors all depend critically on the dielectric constant of the separating insulator or inter-layer dielectric (ILD).
The use of low dielectric constant (k) materials advantageously lowers power consumption, reduces cross-talk, and shortens signal delay for closely spaced conductors through the reduction of both nodal and interconnect line capacitances. Dielectric materials that exhibit low dielectric constants (k) are critical in the development path toward faster and more power efficient microelectronics.
In order to enhance performance of circuit features such as the noted parallel metal lines, a decrease in capacitance may be sought. In order to decrease capacitance the particular ILD employed to isolate the metal lines is often of a ‘low-k’ character. That is, where capacitance (C) is k∈A/d, with a permittivity constant (∈), a distance (d) between the parallel metal lines, and an interfacing area (A) of the metal lines with respect to one another, capacitance (C) may be lowered where the dielectric constant (k) is reduced. As semiconductor features continue to become smaller and smaller, with the distance (d) continuing to be reduced, the use of ‘low-k’ materials in order to reduce capacitance (C) is becoming increasingly important. Generally, a low-k ILD may be an ILD with a dielectric constant (k) that is below about 4.
Siloxanes, particularly cyclosiloxanes, such as 2,4,6,8-tetramethylcyclotetrasiloxane (TMCTS), are being evaluated aggressively for obtaining low-k thin-films as interlayer dielectrics in an integrated circuit by a plasma enhanced chemical vapor deposition (PECVD) approach.
Materials deposited from the cyclosiloxanes result in SiCOH-containing films with Si—CH3 retained in a cross-linking polymeric type networking structure. Generally, Si—CH3 moiety in low-k films is believed to advantageously lower the dielectric constant to values ranging from about 2.4 to 3.2.
The purification and reproducible delivery of these precursor materials for use in PECVD processes is extremely critical for full-scale commercial production. And present deposition processes, specifically with respect to TMCTS suffer from irreproducible delivery due to pre-mature polymerization of the TMCTS precursor within the delivery lines and process hardware.
The premature polymerization reactions occur in heated process environments and/or in the presence of impurities such as water/moisture, Lewis acids and Lewis bases, which with respect to impurities may be introduced into the process environment through various routes such as, raw material synthesis. Manufacture of cyclosiloxanes often results in residual reactants and by-products remaining in the product-stock material, as trace impurities, (e.g. water and partially halogenated or chlorinated silicon species) which if not removed will serve to catalyze the aforementioned polymerization mechanisms in the process delivery lines and hardware.
The PECVD film deposition process environment serves as a further source for the introduction of impurities, where for example, O2 and CO2 containing radicals, generated by the plasma, back-stream into the delivery lines and react with cyclosiloxane molecules to initiate ring-opening and polymerization reactions.
Moreover, catalytic impurities may be introduced to the PECVD process as residual gas species from, for example, a prior cleaning or deposition step. In certain aspects of circuit manufacture, differing steps may be performed on a wafer, in series and in a single PECVD chamber, such as, deposition of a low-k film followed by deposition of a SiN, etch-stop layer. In a typical etch-stop layer deposition step, SiN precursors such as, silanes, chlorosilanes, alkylsilanes, and ammonia (NH3) may be used. And although the CVD tool is purged between steps, residual process gas, particularly ammonia, remains in the process lines, in concentrations sufficient to catalyze the ring-opening and/or polymerization mechanisms of the cyclosiloxane materials in the process hardware and delivery lines.
Accordingly, there is a need in the art to improve the purity of these cyclosiloxane materials by reducing the concentration of water and other catalytic species from therein and to improve their stability and utility during processing in order to minimize the degree to which polymerization occurs in the delivery lines and process hardware.
It would therefore be a significant advance in the art to provide such cyclosiloxane materials and corresponding processes, which are not prone to catalytic polymerization reactions as described hereinabove.